1. Field of the Present Invention
The present invention is related to the field of microprocessors and more particularly to a microprocessor system enabled to gracefully recover from a hang condition.
2. History of Related Art
Advanced microprocessors employ a variety of techniques to aggressively attempt to improve performance. These techniques include the use of multiple execution units, register renaming techniques, as well as speculative and out-of order execution. While potentially improving the performance of a microprocessor, each of these techniques significantly increases the complexity of the microprocessor. As the complexity increases, the ability to simulate the microprocessor""s behavior becomes increasingly expensive and time-consuming. Ultimately, only a portion of the possible states that may occur within the processor are able to be simulated. Accordingly, it is not uncommon to encounter a hang condition in a microprocessor. A hang condition refers to a processor state in which no new instructions are being completed by the processor. Hang conditions may originate from any of a variety of source including, as an example, a live lock condition in which the microprocessor is stuck in an endless state loop. Live lock conditions are well known to those in the field of advanced microprocessor design. When a processor enters a hang condition, the conventional response has been to assert an asynchronous and non-maskable interrupt such as a machine check that essentially terminates operation of the microprocessor. When such a condition is asserted, the user may be required to reboot the system potentially losing a significant amount of information and time. It would therefore be desirable to implement a mechanism suitable for enabling a processor to detect and recover gracefully from a hang condition.
The identified problem is in large part addressed by a processor and an associated method and data processing system. The processor includes an issue unit (ISU), completion unit, and a hang detect unit. The ISU is configured to issue instructions to an execution unit. The completion unit is adapted to produce a completion valid signal responsive to the issue unit completing an instruction. The hang detect unit is configured to receive the completion valid signal from the completion unit and adapted to determine the interval since the most recent assertion of the completion valid signal. The hang detect unit is adapted to initiate a hang recovery sequence upon determining that the interval since the most recent assertion of the completion valid signal exceeds a predetermined maximum interval. In one embodiment, the hang recovery sequence includes the bang recovery unit asserting a stop completion signal to a completion unit and a stop dispatch signal to a dispatch unit to suspend instruction completion and dispatch, the hang recovery unit asserting a force reject signal to an execution unit to reject all instructions pending in the execution unit""s pipeline, the hang recovery unit asserting a flush signal to the execution unit that results in the processor flushing a set of instructions, and the hang recovery unit negating the force reject, stop completion, and stop dispatch signals to resume processor operation. In one embodiment, the recovery sequence includes entering a relaxed execution mode, such as a debug mode, a serial operation mode, or an in-order mode prior to resuming processor operation. In one embodiment, the processor advances a completion tag upon completing an instruction. In this manner the completion tag indicates the instruction that is next to complete. In one embodiment, the hang recovery sequence includes flushing the processor of an instruction set comprising all instructions with tag information greater than the completion tag. In another embodiment, all instructions with tag information greater than or equal to the completion tag are flushed.